52 search results - page 1 / 11 » A delay fault model for at-speed fault simulation and test g... |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
ITC
1999
IEEE
13 years 10 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
EURODAC
1995
IEEE
13 years 9 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
DFT
2003
IEEE
13 years 11 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...