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DAC
2005
ACM
10 years 3 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
ISCAS
2007
IEEE
110views Hardware» more  ISCAS 2007»
9 years 8 months ago
A Novel Active Decoupling Capacitor Design in 90nm CMOS
—On-chip decoupling capacitors (decaps) are generally used to reduce power supply noise. Passive decap designs are reaching their limits in 90nm CMOS technology due to higher ope...
Xiongfei Meng, Karim Arabi, Resve Saleh
VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
10 years 2 months ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
TIM
2010
294views Education» more  TIM 2010»
8 years 9 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
9 years 8 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
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