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VLSID
2005
IEEE
140views VLSI» more  VLSID 2005»
14 years 5 months ago
Variable Resizing for Area Improvement in Behavioral Synthesis
High level synthesis tools transform an algorithmic description to a register transfer language (RTL) description of the hardware. The algorithm behavior is typically described in...
R. Gopalakrishnan, Rajat Moona
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
14 years 5 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
UML
1998
Springer
13 years 9 months ago
Automating the Synthesis of UML StateChart Diagrams from Multiple Collaboration Diagrams
The use of scenarios has become a popular technique for requirements elicitation and specification building. Since scenarios capture only partial descriptions of system behavior, ...
Ismaïl Khriss, Mohammed Elkoutbi, Rudolf K. K...
DAC
1997
ACM
13 years 9 months ago
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...
Claus Schneider