10 search results - page 1 / 2 » ARPIA: A High-Level Evolutionary Test Signal Generator |
EVOW
2001
Springer
13 years 9 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
TVLSI
2008
13 years 4 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
EVOW
2008
Springer
13 years 6 months ago
2008
Springer
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodolo...
ISQED
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
FPL
2001
Springer
13 years 9 months ago
2001
Springer
Abstract. Visual data
ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal
ow gra...