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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 5 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
VLSISP
2008
134views more  VLSISP 2008»
13 years 4 months ago
Calibration of Abstract Performance Models for System-Level Design Space Exploration
ion of Abstract Performance Models for System-Level Design Space Exploration ANDY D. PIMENTEL, MARK THOMPSON, SIMON POLSTRA AND CAGKAN ERBAS Computer Systems Architecture Group, In...
Andy D. Pimentel, Mark Thompson, Simon Polstra, Ca...
ASPDAC
2012
ACM
281views Hardware» more  ASPDAC 2012»
12 years 23 days ago
Abstract system-level models for early performance and power exploration
Andreas Gerstlauer, Suhas Chakravarty, Manan Kathu...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
13 years 10 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
13 years 11 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...