Sciweavers

120 search results - page 1 / 24
» An Accurate Interconnection Length Estimation for Computer L...
Sort
View
GLVLSI
1996
IEEE
126views VLSI» more  GLVLSI 1996»
13 years 10 months ago
An Accurate Interconnection Length Estimation for Computer Logic
Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving p...
Dirk Stroobandt, Herwig Van Marck, Jan Van Campenh...
ICCAD
2005
IEEE
122views Hardware» more  ICCAD 2005»
14 years 2 months ago
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A priori wirelength estimation is concerned with predicting various wirelength characteristics before placement. In this work we propose a novel, accurate estimator of net lengths...
Andrew B. Kahng, Sherief Reda
VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
13 years 10 months ago
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
Andrew B. Kahng, Sudhakar Muddu
DAC
2002
ACM
14 years 6 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 2 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha