4 search results - page 1 / 1 » An On-Chip Jitter Measurement Circuit for the PLL |
ATS
2003
IEEE
13 years 8 months ago
2003
IEEE
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...