10 search results - page 2 / 2 » An automated methodology for memory-conscious mapping of DSP... |
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
ASAP
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...