40 search results - page 1 / 8 » An evolutionary approach to timing driven FPGA placement |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...