117 search results - page 1 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
ICCAD
2003
IEEE
13 years 10 months ago
2003
IEEE
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...