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ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
10 years 1 months ago
Analysis and optimization of gate leakage current of power gating circuits
— Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling dow...
Hyung-Ock Kim, Youngsoo Shin
VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
10 years 8 months ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
ICCAD
2007
IEEE
130views Hardware» more  ICCAD 2007»
10 years 4 months ago
Analysis and optimization of power-gated ICs with multiple power gating configurations
- Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting...
Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh ...
DAC
2005
ACM
10 years 8 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correla...
Hongliang Chang, Sachin S. Sapatnekar
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
10 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
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