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» Architectural energy optimization by bus splitting
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DAC
2000
ACM
14 years 6 months ago
The design and use of simplepower: a cycle-accurate energy estimation tool
In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo...
Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir...
CODES
2005
IEEE
13 years 11 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Physical design implementation of segmented buses to reduce communication energy
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
NOCS
2009
IEEE
14 years 6 days ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
CASES
2001
ACM
13 years 9 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...