16 search results - page 1 / 4 » Block-level 3D IC design with through-silicon-via planning |
DATE
2009
IEEE
14 years 4 days ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
3DIC
2009
IEEE
14 years 6 days ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
VLSI
2010
Springer
13 years 3 months ago
2010
Springer
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
GLVLSI
2009
IEEE
13 years 3 months ago
2009
IEEE
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
ASPDAC
2012
ACM
12 years 1 months ago
2012
ACM
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...