11 search results - page 1 / 3 » Bridge Fault simulation strategies for CMOS integrated Circu... |
DAC
1993
ACM
13 years 9 months ago
1993
ACM
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...