40 search results - page 3 / 8 » Buffering Interconnect for Multicore Processor Designs |
PDP
2010
IEEE
14 years 10 days ago
2010
IEEE
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
14 years 8 days ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
TVLSI
2010
13 years 4 days ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
FPL
2008
Springer
13 years 7 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...