56 search results - page 1 / 12 » Buffering global interconnects in structured ASIC design |
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wire...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
DAC
2009
ACM
13 years 8 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...