Sciweavers

13 search results - page 2 / 3
» CAD computation for manufacturability: can we save VLSI tech...
Sort
View
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
13 years 11 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 2 months ago
A New Statistical Optimization Algorithm for Gate Sizing
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
Murari Mani, Michael Orshansky
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 2 days ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
13 years 11 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
14 years 5 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava