44 search results - page 1 / 9 » Cell selection from technology libraries for minimizing powe... |
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit ...
TCAD
1998
13 years 4 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
TVLSI
2008
13 years 4 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
VLSID
2006
IEEE
13 years 10 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...