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2002
IEEE

A Power Minimization Technique for Arithmetic Circuits by Cell Selection

10 years 11 months ago
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction.
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo,
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2002
Where VLSID
Authors Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
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