44 search results - page 2 / 9 » Cell selection from technology libraries for minimizing powe... |
DATE
2009
IEEE
14 years 1 days ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
VLSID
2008
IEEE
13 years 11 months ago
2008
IEEE
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...
FPL
1997
Springer
13 years 9 months ago
1997
Springer
Technology mapping can be viewed as the optimization problem of finding a minimum cost cover of the given Boolean network by choosing from given library of logic cells. The core of...