7 search results - page 1 / 2 » Clock recovery in high-speed multilevel serial links |
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— This paper presents a passive filter for the front end of a high speed serial link receiver to aid timing recovery. The filter provides simultaneous lowpass and highpass tran...
TVLSI
2010
12 years 12 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...