217 search results - page 1 / 44 » Closed-Form Simulation and Robustness Models for SEU-Toleran... |
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
NN
2002
Springer
2002
Springer
Optimal design of regularization term and regularization parameter by subspace information criterion
13 years 4 months ago
The problem of designing the regularization term and regularization parameter for linear regression models is discussed. Previously, we derived an approximation to the generalizat...