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» Communication Analysis for System-On-Chip Design
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ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
13 years 12 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
GLVLSI
2005
IEEE
120views VLSI» more  GLVLSI 2005»
13 years 11 months ago
3D module placement for congestion and power noise reduction
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
DAC
2006
ACM
13 years 7 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CODES
2009
IEEE
13 years 9 months ago
Building heterogeneous reconfigurable systems with a hardware microkernel
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
Jason Agron, David L. Andrews
FPL
2004
Springer
164views Hardware» more  FPL 2004»
13 years 9 months ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne