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» Communication Mechanisms for Parallel DSP Systems on a Chip
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VLSISP
1998
128views more  VLSISP 1998»
13 years 5 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
ARC
2010
Springer
126views Hardware» more  ARC 2010»
13 years 3 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
NOCS
2009
IEEE
14 years 6 days ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
ISCAS
2005
IEEE
247views Hardware» more  ISCAS 2005»
13 years 11 months ago
Digital signal processing engine design for polar transmitter in wireless communication systems
Polar modulation techniques offer the capability of multimode wireless system and the potential for the high efficiency Power Amplifier (PA). This paper describes a new design of D...
Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
13 years 11 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman