22 search results - page 3 / 5 » Cost-driven 3D integration with interconnect layers |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Detailed electromagnetic analysis of three-dimensional structures in multilayered dielectric media is critical for automatic generation of equivalent circuit models for the interc...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...