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ATS
2009
IEEE
185views Hardware» more  ATS 2009»
13 years 11 months ago
Customized Algorithms for High Performance Memory Test in Advanced Technology Node
Embedded memory quality is critical to overall chip quality. New defect mechanisms that occur at advanced process nodes (65nm and below) are often more pronounced in memories due ...
Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
13 years 10 months ago
BIST for Deep Submicron ASIC Memories with High Performance Application
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Ome...
PVLDB
2010
204views more  PVLDB 2010»
13 years 3 months ago
Cheetah: A High Performance, Custom Data Warehouse on Top of MapReduce
Large-scale data analysis has become increasingly important for many enterprises. Recently, a new distributed computing paradigm, called MapReduce, and its open source implementat...
Songting Chen
HPCA
2009
IEEE
14 years 5 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
13 years 11 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...