13 search results - page 2 / 3 » Customized Reconfigurable Interconnection Networks for multi... |
ERSA
2010
13 years 3 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
MOBIQUITOUS
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper proposes the Middleware for Application Interconnection in Personal Area Networks (MAIPAN), a middleware that provides a uniform computing environment for creating dyna...
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...