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» Defect Tolerance for Nanoscale Crossbar-Based Devices
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DT
2008
63views more  DT 2008»
13 years 5 months ago
Defect Tolerance for Nanoscale Crossbar-Based Devices
Mohammad Tehranipoor, Reza M. Rad
DFT
2004
IEEE
134views VLSI» more  DFT 2004»
13 years 8 months ago
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Defect tolerance is an extremely important aspect in nano-scale electronics as the bottom-up selfassembly fabrication process results in a significantly higher defect density comp...
Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lomb...
FCCM
2006
IEEE
106views VLSI» more  FCCM 2006»
13 years 11 months ago
Defect-Tolerant Nanocomputing Using Bloom Filters
We propose a novel defect-tolerant design methodology using Bloom filters for defect mapping for nanoscale computing devices. It is a general approach that can be used for any pe...
Gang Wang, Wenrui Gong, Ryan Kastner
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 9 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
CODES
2008
IEEE
13 years 6 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...