8 search results - page 1 / 2 » Design and Analysis of Low-Voltage Current-Mode Logic Buffer... |
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...