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FPL
2004
Springer
81views Hardware» more  FPL 2004»
13 years 10 months ago
Design and Implementation of the Memory Scheduler for the PC-Based Router
Tomás Marek, Martin Novotný, Ludek C...
AAAIDEA
2005
IEEE
13 years 10 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou
DAC
2009
ACM
14 years 5 months ago
An SDRAM-aware router for Networks-on-Chip
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilizat...
Wooyoung Jang, David Z. Pan
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
13 years 10 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
HOTI
2005
IEEE
13 years 10 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner