Sciweavers

427 search results - page 3 / 86
» Design and application of multimodal power gating structures
Sort
View
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
DAC
2005
ACM
14 years 6 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
13 years 12 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
ISQED
2006
IEEE
142views Hardware» more  ISQED 2006»
13 years 11 months ago
Constructing Current-Based Gate Models Based on Existing Timing Library
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
Andrew B. Kahng, Bao Liu, Xu Xu
ATS
2005
IEEE
139views Hardware» more  ATS 2005»
13 years 11 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy