59 search results - page 2 / 12 » Design for Verification in System-level Models and RTL |
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
DAC
2007
ACM
13 years 9 months ago
2007
ACM
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
IEICET
2006
13 years 5 months ago
2006
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract: This paper addresses the problem of equivalence veriļ¬cation of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have diļ¬...