122 search results - page 1 / 25 » Designing a Memory Module Tester |
MTDT
1999
IEEE
13 years 9 months ago
1999
IEEE
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
ISVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design method...