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» Deterministic BIST with Partial Scan
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ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 9 months ago
Deterministic partitioning techniques for fault diagnosis in scan-based BIST
A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified...
Ismet Bayraktaroglu, Alex Orailoglu
ITC
1997
IEEE
93views Hardware» more  ITC 1997»
13 years 9 months ago
Fault Diagnosis in Scan-Based BIST
A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the ...
Janusz Rajski, Jerzy Tyszer
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 9 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 9 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
13 years 10 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...