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» Device and Technology Challenges for Nanoscale CMOS
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ICCD
2006
IEEE
148views Hardware» more  ICCD 2006»
14 years 1 months ago
Trends and Future Directions in Nano Structure Based Computing and Fabrication
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
R. Iris Bahar
ISQED
2010
IEEE
127views Hardware» more  ISQED 2010»
13 years 3 months ago
Limits of bias based assist methods in nano-scale 6T SRAM
Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRA...
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Bent...
ICCAD
2005
IEEE
199views Hardware» more  ICCAD 2005»
13 years 10 months ago
FinFETs for nanoscale CMOS digital integrated circuits
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
Tsu-Jae King
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...