38 search results - page 2 / 8 » Device and Technology Challenges for Nanoscale CMOS |
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
TCAD
2008
13 years 5 months ago
2008
As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design chall...
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
ISQED
2009
IEEE
14 years 17 days ago
2009
IEEE
In this paper challenges observed in 65nm technology for circuits utilizing subthreshold region operation are presented. Different circuits are analyzed and simulated for ultra lo...