12 search results - page 1 / 3 » Effective Capacitance Macro-Modelling for Architectural-Leve... |
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
TVLSI
2008
13 years 4 months ago
2008
Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or place...