Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...