7 search results - page 1 / 2 » Efficient and accurate gate sizing with piecewise convex del... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
TCAD
2008
13 years 4 months ago
2008
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...