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TVLSI
2010
13 years 7 days ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2003
ACM
13 years 10 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
DAC
2011
ACM
12 years 5 months ago
Efficient incremental analysis of on-chip power grid via sparse approximation
In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid net...
Pei Sun, Xin Li, Ming Yuan Ting
DAC
2002
ACM
14 years 6 months ago
Communication architecture based power management for battery efficient system design
Communication-based power management (CBPM) is a new batterydriven system-level power management methodology in which the systemlevel communication architecture regulates the exec...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 3 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus