—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...