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ETS
2009
IEEE
98views Hardware» more  ETS 2009»
13 years 3 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
13 years 11 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
13 years 11 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
13 years 9 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
ASPDAC
2005
ACM
96views Hardware» more  ASPDAC 2005»
13 years 8 months ago
Oscillation ring based interconnect test scheme for SOC
- We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, ...