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CODES
2006
IEEE
13 years 11 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
FPL
2005
Springer
73views Hardware» more  FPL 2005»
13 years 10 months ago
Energy-Efficient NoC for Best-Effort Communication
A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energ...
Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Bec...
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
13 years 11 months ago
High-level architecture exploration for MPEG4 encoder with custom parameters
Abstract - this paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted arc...
Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Yo...
PATMOS
2004
Springer
13 years 10 months ago
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the in...
Eric Senn, Johann Laurent, Nathalie Julien, Eric M...
DAC
2012
ACM
11 years 7 months ago
Run-time power-down strategies for real-time SDRAM memory controllers
Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controller...
Karthik Chandrasekar 0001, Benny Akesson, Kees Goo...