57 search results - page 2 / 12 » Evaluation of Applying SpecC to the Integrated Design Method... |
CHI
2009
ACM
14 years 5 months ago
2009
ACM
Jens Gerken HCI Group, University of Konstanz Box D-73 78457 Konstanz, Germany jens.gerken@uni-konstanz.de Hans-Joachim Bieg HCI Group, University of Konstanz Box D-73 78457 Konsta...
DFT
2008
IEEE
13 years 11 months ago
2008
IEEE
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
EDCC
2006
Springer
13 years 8 months ago
2006
Springer
It has been well established that most operating system crashes are due to bugs in device drivers. Because drivers are normally linked into the kernel address space, a buggy drive...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...