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» Exploring adjacency in floorplanning
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ASPDAC
2009
ACM
114views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Exploring adjacency in floorplanning
Jia Wang, Hai Zhou
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Design space exploration for minimizing multi-project wafer production cost
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-...
ASPDAC
2005
ACM
105views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Interconnect estimation without packing via ACG floorplans
Abstract— ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a repre...
Jia Wang, Hai Zhou
ICCD
2004
IEEE
115views Hardware» more  ICCD 2004»
14 years 1 months ago
ACG-Adjacent Constraint Graph for General Floorplans
ACG (Adjacent Constraint Graph) is invented as a general floorplan representation. It has advantages of both adjacency graph and constraint graph of a floorplan: edges in an ACG...
Hai Zhou, Jia Wang
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
14 years 1 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim