22 search results - page 3 / 5 » FPGA Interconnect Delay Fault Testing |
ASPDAC
2006
ACM
14 years 7 hour ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
ET
2002
13 years 5 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
TC
1998
13 years 5 months ago
1998
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
VTS
2006
IEEE
14 years 1 days ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...