21 search results - page 2 / 5 » Fault Diagnosis in Scan-Based BIST |
ITC
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
DFT
2009
IEEE
13 years 12 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
IOLTS
2006
IEEE
13 years 11 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...