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» FinFETs for nanoscale CMOS digital integrated circuits
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ICCAD
2005
IEEE
114views Hardware» more  ICCAD 2005»
14 years 1 months ago
Double-gate SOI devices for low-power and high-performance applications
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhop...
MR
2007
83views Robotics» more  MR 2007»
13 years 4 months ago
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased cu...
Shih-Hung Chen, Ming-Dou Ker
GLVLSI
2008
IEEE
105views VLSI» more  GLVLSI 2008»
13 years 5 months ago
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
13 years 10 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
TIM
2010
294views Education» more  TIM 2010»
12 years 11 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi