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TSP
2008
82views more  TSP 2008»
13 years 4 months ago
Fully Parallel Stochastic LDPC Decoders
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
SIPS
2007
IEEE
13 years 11 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
13 years 10 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
13 years 11 months ago
A dual-core programmable decoder for LDPC convolutional codes
Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This archite...
Marcos B. S. Tavares, Emil Matús, Steffen K...
ICASSP
2011
IEEE
12 years 8 months ago
Multiple LDPC decoding using bitplane correlation for Transform Domain Wyner-Ziv video coding
Distributed video coding (DVC) is an emerging video coding paradigm for systems which fully or partly exploit the source statistics at the decoder to reduce the computational burd...
Huynh Van Luong, Xin Huang, Søren Forchhamm...