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» Gate delay estimation in STA under dynamic power supply nois...
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ASPDAC
2010
ACM
171views Hardware» more  ASPDAC 2010»
13 years 3 months ago
Gate delay estimation in STA under dynamic power supply noise
Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki,...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 2 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
14 years 6 days ago
Decoupling capacitor planning with analytical delay model on RLC power grid
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
Ye Tao, Sung Kyu Lim
ICCD
2004
IEEE
128views Hardware» more  ICCD 2004»
14 years 2 months ago
Static Transition Probability Analysis Under Uncertainty
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
Siddharth Garg, Siddharth Tata, Ravishankar Arunac...
VTS
2005
IEEE
97views Hardware» more  VTS 2005»
13 years 11 months ago
Static Compaction of Delay Tests Considering Power Supply Noise
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, ...